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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Some of contents are subject to change without notice. PIN CONFIGURATION (TOP VIEW)
Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10 A0 A1 A2 A3 Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss
DESCRIPTION
The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S30ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems.
FEATURES
- Single 3.3v0.3v power supply - Clock frequency 125MHz /100MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/Full Page (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Burst Write / Single Write (programmable) - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms - Column address A0-A8 - LVTTL Interface - 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
Max. Frequency M5M4V64S30ATP-8A M5M4V64S30ATP-8 M5M4V64S30ATP-10 125MHz 100MHz 100MHz CLK Access Time 6ns 6ns 8ns
CLK CKE /CS /RAS /CAS /WE DQ0-7 DQM A0-11 BA0,1 Vdd VddQ Vss VssQ
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Output Disable/ Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output
400mil 54pin TSOP(II)
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
DQ0-7
BLOCK DIAGRAM
I/O Buffer
Memory Array Memory Array Memory Array Memory Array Bank #0 Bank #1 Bank #2 Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer
Control Signal Buffer
A0-11 BA0,1
/CS /RAS /CAS /WE DQM
CLK
CKE
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 5M 4 V 64 S 3 0 A TP - 8
Access Item Package Type TP: TSOP(II) Process Generation Function 0: Random Column, 1: 2N-rule Organization 2n 2: x4, 3: x8, 4: x16 Synchronous DRAM Density 64:64M bits Interface S: SSTL, V:LVTTL Memory Style (DRAM) Use, Recommended Operating Conditions, etc Mitsubishi Main Designation
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
PIN FUNCTION
CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-8 . A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data In and Data out are referenced to the rising edge of CLK. Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is masked. When DQM is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry. VddQ and VssQ are supplied to the Output Buffers only.
CKE
Input
/CS /RAS, /CAS, /WE
Input Input
A0-11
Input
BA0,1 DQ0-7 DQM Vdd, Vss VddQ, VssQ
Input Input / Output Input Power Supply Power Supply
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
BASIC FUNCTIONS
The M5M4V64S30ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.
CLK /CS /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA). Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (autoprecharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with AutoPrecharge Column Address Entry & Read Column Address Entry & Read with AutoPrecharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE n-1 H H H H H H CKE n X X X X X X /CS H L L L L L /RAS /CAS X H L L L H X H H H H L /WE X H H L L L BA0,1 X X V V X V A11 X X V X X X A10 X X V L H L A0-9 X X V X X V
WRITEA
H
X
L
H
L
L
V
X
H
V
READ
H
X
L
H
L
H
V
X
L
V
READA REFA REFS REFSX TBST MRS
H H H L L H H
X H L H H X X
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X L
X X X X X X L
H X X X X X L
V X X X X X V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE
Current State IDLE /CS H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS X H H H L L L L X H H H H L L L L X H H H /CAS X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 Address Command DESEL NOP TBST NOP NOP ILLEGAL*2 Action
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst
Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
L L L L L
H L L L L
L H H L L
L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State WRITE /CS H L L L /RAS X H H H /CAS X H H L /WE X H L H X X BA BA, CA, A10 Address Command DESEL NOP TBST Action NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst
Terminate Burst, Latch CA, READ / READA Begin Read, Determine AutoPrecharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST WRITE / WRITEA ACT PRE / PREA REFA MRS ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
READ / READA ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State PRE CHARGING /CS H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS X H H H L L L L X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State REFRESHING /CS H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle*3 Exit CLK Suspend at Next Cycle*3 Maintain CLK Suspend Action
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX
MODE REGISTER SET
MRS
IDLE
REFA
AUTO REFRESH
CKEL
CLK SUSPEND
CKEL CKEH TBST (for Full Page)
CKEH ACT
POWER DOWN
ROW ACTIVE
TBST (for Full Page)
WRITE WRITEA READA READ WRITE
READ
CKEL
CKEL
WRITE SUSPEND
WRITE
CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA CKEL READA
READA
CKEL
WRITEA SUSPEND
WRITEA
PRE
PRE PRE
READA
CKEH
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
PRE
PRE CHARGE Automatic Sequence Command Sequence
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200s. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are inA@ idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
CLK /CS /RAS /CAS /WE BA0,1 A11-A0 BA0 BA1 A11 A10 A9 0 0 0 0 A8 A7 A6 0 A5 A4 A3 BT A2 A1 A0 BL
V
WM 0
LTMODE
LATENCY MODE
CL 000 001 010 011 100 101 110 111 0 1
/CAS LATENCY R R 2 3 R R R R BURST SINGLE BIT
BL 000 001 010 011 100 101 110 111
BT= 0 1 2 4 8 R R R FP
BT= 1 1 2 4 8 R R R R
BURST LENGTH
WRITE MODE
BURST TYPE
0 SEQUENTIAL INTERLEAVED 1 R: Reserved for Future Use FP: Full Page
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
CLK Command Address DQ CL= 3 BL= 4 /CAS Latency
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
Burst Length Burst Type
Burst Length
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 A0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 2 1 1 0 2 3 0 3 0 1 0 1 1 2 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 0 1 2 3 1 2 3 4 2 3 4 5 Sequential 3 4 5 6 4 5 6 7 5 6 7 0
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
[ /CAS LATENCY ]
/CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the speed of CLK determines which CL should be used. First output data is available after CL cycles from READ command. /CAS Latency Timing(BL=4)
CLK Command
ACT tRCD
READ
Address
X
Y CL=2
DQ DQ
Q0
Q1
Q2
Q3
CL=2
Q3
CL=3
Q0
Q1
Q2
CL=3
[ BURST LENGTH ]
The burst length, BL, determines the number of consecutive writes or reads that will be automatically performed after the initial write or read command. For BL=1,2,4,8, the output data is tristated (Hi-Z) after the last read. For BL=FP (Full Page), the TBST (Burst Terminate) command must be used to stop the output of data. Burst Length Timing( CL=2 )
tRCD CLK
Command
ACT
READ
Address DQ DQ DQ DQ DQ
X
Y Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Qm Q0 Q1 BL=1 BL=2 BL=4 BL=8 BL=FP
M5M4V64S20A : m=1023 M5M4V64S30A : m=511 M5M4V64S40A : m=255
Full Page counter rolls over and continues to count.
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A11-0. The minimum activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC, although the number of banks which are active concurrently is not limited. PRECHARGE The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued. Bank Activation and Precharge All (BL=4, CL=3)
CLK
2 ACT command / tRCmin tRCmin
Command A0-9 A10 A11 BA0,1 DQ
ACT tRRD Xa
ACT READ tRAS Xb tRCD Xb Xb 01 00 Qa0 Y 0
PRE tRP
ACT Xb
Xa Xa 00
1
Xb Xb 01
Qa1
Qa2
Qa3
READ After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A8-0(X8), A9-0(X4) and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA.
Precharge all
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM Multi Bank Interleaving READ (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1 DQ
/CAS latency ACT tRCD Xa Xa Xa 00 00 Y 0 Xb Xb Xb 10 Qa0 10 Qa1 00 Qa2 Qa3 Qb0 Qb1 Qb2 Y 0 0 READ ACT READ PRE
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CLK
BL + tRP
Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00
READ BL Y 1 tRP
ACT Xa Xa Xa
00 Qa0 Qa1 Qa2 Qa3
00
Internal precharge start
READ Auto-Precharge Timing (BL=4)
CLK Command CL=3 CL=2 DQ DQ
Qa0 ACT READ BL Qa0 Qa1 Qa2 Qa3
Qa1
Qa2
Qa3
Internal Precharge Start Timing
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A8-0 (x 8), A9-0 (x 4), and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the autoprecharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing. The Mode Register can be programmed for burst read and single write. In this mode the write data is only clocked in when the WRITE command is issued and the remaining burst length is ignored. The read data burst length os unaffected while in this mode Multi Bank Interleaving WRITE (BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00 00 Da0 Y 0 Xb Xb Xb 10 Da1 Da2 Da3 10 Db0 Write ACT tRCD Y 0 0 0 00 Db1 Db2 Db3 0 0 10 Write PRE PRE
WRITE with Auto-Precharge (BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00 00 Da0 Da1 Da2 Da3 Internal precharge starts Y 1 Write tWR tRP Xa Xa Xa 00 ACT
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
[ BURST WRITE ]
A burst write operation is enabled by setting A9=0. A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1,2,4,8, and full-page, like burst read operations.
tRCD
CLK
Command
ACT
WRITE
Address DQ DQ DQ DQ DQ
X
Y Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q9 Q10 Qm Q0 Q1 BL=1 BL=2 BL=4 BL=8 BL=FP
M5M4V64S20A : m=1023 M5M4V64S30A : m=511 M5M4V64S40A : m=255
Full Page counter rolls over and continues to count.
[ SINGLE WRITE ]
A single write operation is enabled by setting A9=1. In a single write operation, data is only written to the column address specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0.)
CLK Command
ACT tRCD
WRITE
Address
X
Y
DQ
Q0
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. Read Interrupted by Read (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1 DQ
00 00 10 Qai0 Qaj0 01 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3 READ READ Yi 0 Yj 0 READ Yk 0 READ Yl 0
[ Read Interrupted by Write ] Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1 DQM Q D
Qai0 Daj0 Daj1 Daj2 Daj3 00 00 READ Yi 0 Write Yj 0
DQM control Write control
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
[ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4. Read Interrupted by Precharge (BL=4)
CLK
Command DQ Command
READ
PRE Q0 Q1 Q2
READ
PRE Q0 Q1
CL=3
DQ Command DQ
READ PRE Q0
Command DQ Command
READ Q0 READ PRE Q0
PRE Q1 Q2
CL=2
DQ Command DQ
READ PRE
Q1
Q0
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
[ Read Interrupted by Burst Terminate ]
Similar to a precharge, the burst terminate command, TBST, can interrupt the burst read operation and disable the data output. The READ to TBST interval is a minimum of one CLK. TBST is mainly used to interrupt FP bursts. The figures below show examples, of how the output data is terminated with TBST. Read Interrupted by Burst Terminate(BL=4)
CLK Command DQ
READ TBST
Q0
Q1
Q2
Q3
CL=3
Command DQ
READ
TBST
Q0
Q1
Q2
Command DQ
READ TBST
Q0
Command DQ
READ
TBST
Q0
Q1
Q2
Q3
CL=2
Command DQ
READ
TBST
Q0
Q1
Q2
Command DQ
READ TBST
Q0
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
[ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write Interrupted by Write (BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQ
00 Dai0 00 Daj0 Daj1 10 00 Dal1 Dal2 Dal3 Write Write Yi 0 Yj 0 Write Yk 0 Write Yl 0
Dbk0 Dbk1 Dbk2 Dal0
[ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care". Write Interrupted by Read (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1 DQM DQ
Dai0 Qaj0 Qaj1 Dbk0 Dbk1 Qal0 00 00 10 00 Write READ Yi 0 Yj 0 Write Yk 0 READ Yl 0
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
[ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank . Random column access is allowed. Write recovery time (tWR) is required from the last data to PRE command. Write Interrupted by Precharge (BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQM DQ
Dai0 Dai1 Dai2 00 00 Write tWR Yi 0 0 PRE tRP Xb Xb Xb 00 ACT
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can be used to terminate a burst write operation. In this case, the write recovery time is not required and the bank remains active (Please see the waveforms below). The WRITE to TBST minimum interval is one CLK.
Write Interrupted by Burst Terminate(BL=4)
CLK Command A0-9 A10 BA
DQMU/DQML (DQM) WRITE TBST
Yi
0
0
DQ
Dai0
Dai1
Dai2
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command. Auto-Refresh
CLK /CS NOP or DESELECT /RAS /CAS /WE CKE A0-11 BA0,1 minimum tRC
Auto Refresh on All Banks
Auto Refresh on All Banks
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh
CLK
Stable CLK
/CS /RAS /CAS /WE CKE
NOP
tSRX
new command X 00
A0-11 BA0,1
Self Refresh Entry
Self Refresh Exit
minimum tRC +1 CLOCK for recovery
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CLK CKE Command
PRE NOP NOP Standby Power Down
NOP NOP NOP
NOP NOP
CKE Command
ACT NOP NOP
Active Power Down
NOP NOP NOP
NOP NOP
DQ Suspend by CKE
CLK CKE Command
Write READ
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
DQM CONTROL DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM masks input data word by word. DQM to write mask latency is 0. During reads, DQM forces output to Hi-Z word by word. DQM to output Hi-Z latency is 2.
DQM Function
CLK Command DQM
Write READ
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQM=H
disabled by DQM=H
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VddQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta = 25 C Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ Vdd+0.5 -0.5 ~ VddQ+0.5 50 1000 0 ~ 70 -65 ~ 150 Unit V V V V mA mW C C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70C, unless otherwise noted)
Limits Symbol Vdd Vss VddQ VssQ VIH VIL Note:* Parameter Min. Supply Voltage Supply Voltage Supply Voltage for Output Supply Voltage for Output High-Level Input Voltage all inputs Low-Level Input Voltage all inputs 3.0 0 3.0 0 2.0 -0.3 Typ. 3.3 0 3.3 0 Max. 3.6 0 3.6 0 Vdd+0.3 0.8 V V V V V V Unit
VIH (max) = Vdd+2.0V AC for pulse width<=3ns acceptable. VIL(min) = -2V AC for pulse width<=3ns acceptable.
CAPACITANCE
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CLK pin Input Capacitance, I/O pin Test Condition VI=Vss f=1MHz Vi=25mVrms min. 2.5 2.5 2.5 4 max. 5 5 4 6.5 Unit pF pF pF pF
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, Output Open, unless otherwise noted)
Limits (max) Symbol Parameter Test Conditions -8A Icc1s Icc1d Icc2h Icc2l Icc3h Icc3l Icc4 Icc5 operating current, single bank operating current, dual bank standby current, CKE=H standby current, CKE=L active standby current, CKE=H active standby current, CKE=L burst current auto-refresh current tRC=min, tCLK=min, BL=1, CL=3 tRC=90ns, tCLK=min, BL=1, CL=3 all banks idle, tCLK=min all banks idle, tCLK=min all banks active, tCLK=min all banks active, tCLK=min all banks active, tCLK=min, BL=4, CL=3 tRC=min, tCLK=min -8A,-8,-10 Icc6 self-refresh current CKE <0.2v -8L,-10L 110 135 25 2 55 5 135 150 1 -8L -8 110 115 22 2 55 5 115 150 1 0.5 -10L -10 85 115 22 2 45 2 115 115 1 0.5 Unit
mA mA mA mA mA mA mA mA mA mA
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits Symbol Parameter Test Conditions Min. VOH (DC) High-Level Output Voltage (DC) VOL (DC) IOZ Low-Level Output Voltage (DC) Off-state Output Current Input Current IOH=-2mA IOL= 2mA Q floating VO=0 ~ VddQ VIH = 0 ~ VddQ+0.3V -5 -5 2.4 0.4 5 5 Max. V V A A Unit
II
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V
Limits Symbol Parameter -8A Min. CL=2 tCLK tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tCCD tRSC tSRX tREF Note:1 2 CLK cycle time CL=3 CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time (all inputs) Input Hold time (all inputs) Row Cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Delay time Col to Col Delay time Mode Register Set Cycle time Self Refresh Exit time Refresh Interval time 8 3 3 1 2 1 72 20 48 20 10 16 8 16 8 64 100K 10 10 3 3 1 2 1 70 20 50 20 10 20 10 20 10 64 100K 10 10 4 4 1 3 1 90 30 60 30 10 20 10 20 10 64 100K 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 2 12 Max. -8L,-8 Min. 15 Max. -10L, -10 Min. 15 Max. ns Unit note
1 1 1 1
The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be added to the parameter. 2 ACT commands are allowed within tRC.
CLK Signal
1.4V 1.4V
Any AC timing is referenced to the input signal crossing through 1.4V.
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted see note3)
Limits Symbol Parameter Min. CL=2 tAC Access time from CLK CL=3 tOH Output Hold time from CLK Delay time, output low impedance from CLK Delay time, output high impedance from CLK 2.5 6 3 6 3 8 ns ns -8A Max. 8 -8L,-8 Min. Max. 9 -10L, -10 Min. Max. 9 ns Unit
tOLZ
0
0
0
ns
tOHZ Note:3
2.5
6
3
6
3
8
ns
If tr(clock rising time) is longer than 1ns, (tT/2-0.5)ns should be added to the parameter.
Output Load Condition
VTT=1.4V 50 VREF =1.4V
CLK
1.4V
DQ
VOUT 50pF
1.4V
Output Timing Measurement Reference Point
CLK
1.4V
DQ
tAC tOH
tOHZ
1.4V
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Burst Write (single bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE
tWR
CKE DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0
X Y X Y
X
X
X
X
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
tRAS
tRP tRCD
/RAS
tRCD
/CAS /WE
tWR tWR
CKE DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0
X X Y Y X X Y
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Burst Read (single bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE CKE DQM
DQM read latency =2
A0-8 A10 A9,11 BA0,1 DQ
X
Y
X
Y
X
X
X
X
0
0
0
0
0
CL=3
Q0 Q0 Q0 Q0 Q0 Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ to PRE BL allows full data out
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Burst Read (multiple bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRAS tRP tRCD tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency =2
A0-8 A10 A9,11 BA0,1 DQ
X
X
Y
Y
X
X
Y
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
2
0
CL=3
Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1 Q0
ACT#0
READ#0 ACT#1
PRE#0 READ#1
ACT#0 PRE#1
READ#0 ACT#2
Italic parameter indicates minimum case
35
MITSUBISHI ELECTRIC
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD BL-1+ tWR + tRP BL-1+ tWR + tRP tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0 ACT#1
X X Y Y X Y X Y
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
1
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
D1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1
WRITE#1
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD BL+tRP BL+tRP tRCD
/CAS /WE CKE DQM
DQM read latency =2
A0-8 A10 A9,11 BA0,1 DQ
X
X
Y
Y
X
Y
X
Y
X
X
X
X
X
X
X
X
0
1
0
1
0
0
1
1
CL=3
Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1
CL=3
Q0 Q0
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Page Mode Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0
X X Y Y Y Y
X
X
X
X
0
1
0
0
1
0
D0
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency=2
A0-8 A10 A9,11 BA0,1 DQ
X
X
Y
Y
Y
Y
X
X
X
X
0
1
0
0
1
0
CL=3
Q0 Q0
CL=3
Q0 Q0 Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1
ACT#0
READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
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SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Write Interrupted by Write / Read @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD tCCD
/CAS /WE CKE
DQM A0-8 A10 A9,11 BA0,1 DQ
X X Y Y Y Y Y
X
X
X
X
0
1
0
0
0
1
0
CL=3
D0 D0 D0 D0 D0 D0 D1 D1 Q0 Q0 Q0 Q0
ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
40
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Read Interrupted by Read / Write @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM
DQM read latency=2
A0-8 A10 A9,11 BA0,1 DQ
X
X
Y
Y
Y
Y
Y
Y
X
X
X
X
0
1
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
41
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Write Interrupted by Precharge @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
X X Y Y X Y
X
X
X
X
X
X
0
1
0
1
0
1
1
1
D0
D0
D0
D0
D1
D1
D1
D1
D1
ACT#0 WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted by Precharge of the other bank.
Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
42
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Read Interrupted by Precharge @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD tRP
/RAS
tRCD tRCD
/CAS /WE CKE DQM
DQM read latency=2
A0-8 A10 A9,11 BA0,1 DQ
X
X
Y
Y
X
Y
X
X
X
X
X
X
0
1
0
1
0
1
1
1
Q0
Q0
Q0
Q0
Q1
Q1
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read is not interrupted by Precharge of the other bank.
Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
43
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Mode Register Setting
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRC
tRSC
/RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
Auto-Ref (last of 8 cycles) Mode Register Setting ACT#0
0 M X Y
X
X
0
0
D0
D0
D0
D0
WRITE#0
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
44
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Auto-Refresh @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRC
/RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
Auto-Refresh Before Auto-Refresh, all banks must be idle state. ACT#0
X Y
X
X
0
0
D0
D0
D0
D0
WRITE#0
After tRC from Auto-Refresh, all banks are idle state. Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
45
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Self-Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
CLK can be stopped tRC
/CS /RAS /CAS /WE
tSRX
CKE
CKE must be low to maintain Self-Refresh
DQM A0-8 A10 A9,11 BA0,1 DQ
Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state. Self-Refresh Exit After tRC from Self-Refresh Exit, all banks are idle state. Italic parameter indicates minimum case ACT#0
X
X
X
0
MITSUBISHI ELECTRIC
46
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
DQM Write Mask @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0
X Y Y Y
X
X
0
0
0
0
masked
D0 D0 D0 D0 D0 D0 D0
masked
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
47
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
DQM Read Mask @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
DQM read latency=2
DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0 READ#0
X Y Y Y
X
X
0
0
0
0
masked
Q0 Q0 Q0 Q0
masked
Q0 Q0 Q0
READ#0
READ#0
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
48
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS /CAS /WE
Standby Power Down
CKE
CKE latency=1
Active Power Down
DQM A0-8 A10 A9,11 BA0,1 DQ
Precharge All ACT#0
X
X
X
0
Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
49
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
CLK Suspend @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
CKE latency=1 CKE latency=1
DQM A0-8 A10 A9,11 BA0,1 DQ
ACT#0
X Y Y
X
X
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
WRITE#0 READ#0 CLK suspended
CLK suspended Italic parameter indicates minimum case
MITSUBISHI ELECTRIC
50
SDRAM (Rev.1.3) Mar'98
MITSUBISHI LSIs
M5M4V64S30ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.All information contained in these materials,including product data, diagrams and charts,represent information on products at the time of DQM publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product A0-8 distributor for the latest product information before purchasing a product listed herein.
A10 manufactured for use in a device or system that is used under
4.Mitsubishi Electric Corporation semiconductors are not designed or
circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein A9,11 for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
MITSUBISHI ELECTRIC
51

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